1. Field of the Invention
The present invention relates to a power semiconductor device and, more particularly, to a power semiconductor device of a transfer mold resin sealing type which can miniaturize and reduce cost of the power semiconductor device and which can also miniaturize a printed wiring board connected to the power semiconductor device.
2. Description of the Background Art
A power semiconductor device generally operates under a large current and high voltage, and therefore it is important to miniaturize and reduce cost of such a power module while decreasing thermal resistance and securing high insulating performance.
For example, as disclosed in Japanese Patent Application Laid-Open No. 11-204724 (1999), there is a structure in which power semiconductor elements are mounted on lead frames on which wiring patterns of a predetermined electrical circuit are formed, one surface of a metal substrate formed with an aluminum plate or copper plate, a high thermally-conductive insulating layer and a copper foil is soldered, and then the entirety is sealed by a transfer mold resin such that the other surface of the metal substrate is exposed. This structure miniaturizes and reduces cost of a power module of a transfer mold resin sealing type, and simplifies manufacturing steps.
The conventional technique disclosed in Japanese Patent Application Laid-Open No. 11-204724 (1999) realizes a miniaturized power semiconductor device, and miniaturizes and reduces cost of the power semiconductor device by using lead frames formed with punching press and providing a high thermally-conductive metal substrate directly below the lead frames on which the power semiconductor elements are mounted. However, this conventional technique adopts a structure which cannot provide a satisfying effect as a structure for realizing a miniaturized power semiconductor device at reduced cost.
That is, the power semiconductor device of a transfer mold resin sealing type using a lead frames according to the conventional technique adopts a structure which can take out lead frames which serve as terminals, only from a side surface peripheral direction of the power semiconductor device because of the transfer step, and, after the device is sealed with a transfer mold resin, it is necessary to cut a tie bar part of the lead frames for separating various electrodes, and perform bending processing of the lead parts which are external terminals to be mounted on the printed wiring board.
Further, metals of the external terminals formed with these leads are exposed and are not insulated. Therefore, it is necessary to secure an insulating distance between the external terminals, and, even if a mold resin sealing part on which the power semiconductor element is mounted and sealed is miniaturized, the size of the power semiconductor device is defined according to the insulating distance between the external terminals for securing the insulating distance between lead external terminals projecting from side surfaces, and therefore miniaturization is limited.
As one solution for this problem, a method of taking out external terminals from the upper surface of the power semiconductor device is possible. That is, a method of arranging external electrodes in the surface is possible. This method is applied to recent light electrical semiconductor devices, and, taking into account this idea, area array packages such as PGA packages in which pin electrodes made of metal are formed on a surface instead of lead frames are being developed.
That is, it is possible to miniaturize a semiconductor device by arranging external terminals on a planar surface. By applying this method to a power semiconductor device, external terminals can be taken out while maintaining the insulating distance in the planar surface, so that it is possible to miniaturize the power semiconductor device.
However, external terminals are formed directly above the surface of the power semiconductor device, and therefore the positions to take out the external terminals largely depend on the layout of the power semiconductor elements in the power semiconductor device and drawing of a pattern of a printed wiring board bonded with a power semiconductor device by the external terminals become complicated, and, there is a problem that flexibility of pattern design of the printed wiring board is lost and the printed wiring board becomes large.